Field of the Invention
The invention relates to a memory cell configuration and a method for producing the memory cell configuration.
Memory cell configurations, both for DRAM applications and for non-volatile memories, have an increased storage density from generation to generation.
In DRAM cell configurations, use is made almost exclusively of so-called single-transistor memory cells. A single-transistor memory cell includes a read-out transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge, which represents a logic value, zero or one. That information can be read out through a bit line by driving the read-out transistor through a word line. The storage capacitor must have a minimum capacitance in order to reliably store the charge and at the same time be able to distinguish between the information read out. The lower limit for the capacitance of the storage capacitor is currently regarded as 20 fF.
Since the storage density increases from memory generation to memory generation, the required area of the single-transistor memory cell must be reduced from generation to generation. At the same time, the minimum capacitance of the storage capacitor must be maintained.
Up until the 1 Mbit generation, both the read-out transistor and the storage capacitor were realized as planar components. Starting with the 4 Mbit memory generation, a further deduction in the area of the memory cell was achieved through the use of a three-dimensional configuration of the read-out transistor and the storage capacitor. One possibility is to realize the storage capacitor in a trench. In that case, the electrodes of the storage capacitor are disposed along the surface of the trench. That increases the effective area of the storage capacitor, upon which the capacitance depends, as compared with the space requirement at the surface of the substrate for the storage capacitor, which corresponds to the cross-section of the trench.
A further possibility for increasing the storage capacitance with the space requirement of the storage capacitor remaining the same or being reduced is constructing the storage capacitor as a stacked capacitor. In that case, a polysilicon structure, for example a cylinder, a crown structure or a rib structure (FIN), is formed over the word lines and makes contact with the substrate. That polysilicon structure forms the storage node. It is provided with a capacitor dielectric and a capacitor plate. In that case, the free space above the substrate surface is utilized for the storage capacitor. The entire cell area can be covered by the polysilicon structure as long as the polysilicon structures for adjacent memory cells are insulated with respect to one another. That concept has the advantage of being largely compatible with a logic process.
The area for a memory cell of a DRAM belonging to the 1 Gbit generation should only be about 0.2 .mu.m.sup.2. In order to realize the minimum capacitance for the storage capacitor of approximately 25 fF on an area of that type, it is necessary, in the case of a trench capacitor concept, for the active trench depth to be at least 8 .mu.m in conjunction with a trench width of 0.3 .mu.m and a dielectric having an oxide-equivalent thickness of 4 nm. Trenches having dimensions of that type can only be realized by using complicated etching processes with long etching times. In a stacked capacitor concept, those demands on the area requirement of a memory cell can only be realized with a relatively complicated structure of the polysilicon structure. In addition, those complicated structures are more and more difficult to produce due to their topology.
A further increase in the capacitance that can be attained per unit of area is achieved by the use of so-called high-epsilon dielectrics as a storage dielectric in the storage capacitor (see, for example, the paper by P. C. Fazan, entitled: Trends in, the Development of ULSI DRAM Capacitors, in Integrated Ferroelectrics, Volume 4 (1994), pages 247 to 256). High-epsilon dielectrics are ferroelectric or paraelectric materials. The capacitor is constructed as a stacked capacitor in those concepts. To that end, a lower electrode is first produced by layer deposition and structuring. The high-epsilon dielectric is deposited thereon. Finally, an upper capacitor electrode is applied, structured and provided with an electrical contact. Since high-epsilon dielectrics are deposited at temperatures in the range of 700 to 800.degree. C., at which many electrode materials react, only specific materials, for example TiN, Pt, W, RuO.sub.2, Ir.sub.2 O.sub.3 or Pd, are suitable for the lower electrodes. The search for further materials which are suitable for the lower electrode is the subject of worldwide research activity.